QSFP+ 40G LR4 10KM

The HANSUN QSFP+ 40G-LR4-10km module is a highly integrated 4x10G transceiver focused on reach, bandwidth, density and cost for high port-count 40G systems, and client-side 40G interfaces. The 40G QSFP+ LR4 Lite transceiver is designed for applications based on the IEEE802.3ba 40GBASE-LR4 standard of up to 10km reach.

Specifications of QSFP+ 40G LR4 10km

Optical Transmitter Performance

Parameter	Symbol	Min	Typical	Max	Unit
Center Wavelength	Ch0	λ0	1264.5	–	1277.5	nm
Ch1	λ1	1284.5	–	1297.5	nm
Ch2	λ2	1304.5	–	1317.5	nm
Ch3	λ3	1324.5		1337.5	nm
Bit Rate per Channel	B	10.3125		10.7546	Gb/s
Total Average Launch Power	POUT	–	–	8.0	dBm
Side Mode Suppression Ratio	SMSR	30	–	–	dB
Average launch power, each lane		-6.8	–	2.0	dBm
Optical Modulation Amplitude (each lane)	OMA	-3.8	–	3.5	dBm
Optical Modulation Amplitude (OMA) – TDP, per lane (min)	–	-4.8	–	–	dBm
Transmission & dispersion penalty,each lane	TDP	–	–	2.3	dB
RIN12 OMA	–	–	–	-128	dB/Hz
Transmitter Reflectance	–	–	–	-12	dB
Extinction Ratio	ER	3.5	–		dB
Transmitter eye mask definition {X1, X2, X3, Y1, Y2, Y3}	{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}
Average launch power of OFF transmitter, each lane	–	–	–	-30	dBm
Optical return loss tolerance	–	–	–	20	dB

Optical Receiver Performance

Parameter	Symbol	Min	Typical	Max	Unit
Center Wavelength	λ0	1264.5	1271	1277.5	nm
Ch1	λ1	1284.5	1291	1297.5	nm
Ch2	λ2	1304.5	1311	1317.5	nm
Ch3	λ3	1324.5	1331	1337.5	nm
Bit Rate per Channel	B	10.3125	–	10.7546	Gb/s
Damage threshold, each lane	–	3.4	–	–	dBm
Average receive power, each lane	–	-13.5	–	2.0	dbm
Unstressed Sensitivity (OMA) at 10 x 10-12BER	OMAin	–	–	-11.5	dBm
Stressed Sensitivity (OMA)	OMAin,str	–	–	-9.9	dBm
Receiver Reflectance	ORL	–	–	-26	dB
Vertical eye closure penalty, each lane	VECP	–	–	1.6	dB
Receive electrical 3 dB upper cutoff frequency, per lane	–	–	–	12.3	GHZ
Stressed eye J2 Jitter, each lane	J2	–	–	0.42	UI
Stressed eye J9 Jitter, each lane	J9	–	–	0.65	UI
Eye mask coordinates #1 {X1, X2 Y1, Y2} Hit ratio = 5 x 10E-5	{ 0.29, 0.5 150, 425}

40G Ethernet
InfiniBand QDR and DDR interconnects

Pin	Symbol	Name/Description
1	GND	Ground
2	Tx2n	Transmitter Inverted Data Input
3	Tx2p	Transmitter Non-Inverted Data Input
4	GND	Ground
5	Tx4n	Transmitter Inverted Data Input
6	Tx4p	Transmitter Non-Inverted Data Input
7	GND	Ground
8	ModSelL	Module Select
9	ResetL	Module Reset
10	Vcc Rx	+3.3 V Power supply receiver
11	SCL	2-wire serial interface clock
12	SDA	2-wire serial interface data
13	GND	Ground
14	Rx3p	Receiver Non-Inverted Data Output
15	Rx3n	Receiver Inverted Data Output
16	GND	Ground
17	Rx1p	Receiver Non-Inverted Data Output
18	Rx1n	Receiver Inverted Data Output
19	GND	Ground
20	GND	Ground
21	Rx2n	Receiver Inverted Data Output
22	Rx2p	Receiver Non-Inverted Data Output
23	GND	Ground
24	Rx4n	Receiver Inverted Data Output
25	Rx4p	Receiver Non-Inverted Data Output
26	GND	Ground
27	ModPrsL	Module Present
28	IntL	Interrupt
29	Vcc Tx	+3.3 V Power supply transmitter
30	Vcc1	+3.3 V Power Supply
31	LPMode	Low Power Mode
32	GND	Ground
33	Tx3p	Transmitter Non-Inverted Data Input
34	Tx3n	Transmitter Inverted Data Input
35	GND	Ground
36	Tx1p	Transmitter Non-Inverted Data Input
37	Tx1n	Transmitter Inverted Data Input
38	GND	Ground

Important Notice of QSFP+ 40G LR4 10km

Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by T&S before they become applicable to any particular order or contract. In accordance with the T&S policy of continuous improvement specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of T&S or others. Further details are available from any T&S sales representative.